HartRAO NCCS Updates

1. PC-STEER hardware cage -
   • the demultiplexor board prototype has been tested using test software on PC-STEER and works ! Minor modifications/improvements are presently being made as experience is gained with the prototype

2. device servers -
   • the first real device server for doing low-level SDIO input/output is written and has been tested successfully

1. PC-STEER hardware cage -
   • the timer board prototype is under test, minor bugs in the hardware and microcode are being corrected, most of the board is working and it correctly decodes NASA time and latches the other boards e.g. counter,
   • the counter board prototype has been tested together with the V/F prototype and debugging is presently going on.

2. PC-CORREL -
   • a cable and simulator have been built and are now ready for testing, the simulator will enable the software to be tested without the correlator,
   • an Ethernet card with packet driver has been ordered.

3. System software -
   • the scheduler has been designed and is now awaiting implementation,
   • the interactive scripting language which is based on tcl is starting to be implemented, the first commands for talking to device servers directly have been implemented.

1. PC-STEER hardware cage -
   • the counter card prototype is now working. A final test remains to be done with a precise input frequency to calibrate the blanking period.
   • the timer card prototype is also working and awaits only a minor modification to the microcode adding support for digital radiometry,
   • the digital input/output card prototype has been wired and checked in the lab and is now ready to be tested in the cage

2. PC-CORREL -
   • a simulator for PC-CORREL with some LEDS to indicate the status of the correlator bits and switches to simulate readable data,
   • an Ethernet card with suitable packet driver was ordered and has arrived. The new card will go into an existing Pentium and the old Western Digital card will go into PC-CORREL,

1. PC-STEER hardware cage -
   • the analog/digital and digital/analog boards are at the design stage,
   • a 1PPS output is to be added to the timer prototype card.
   • the counter card prototype was checked against a standard frequency source and found to be accurate to within 1 cycle.

2. Fast data acquisition -
   • the board layout of the voltage/frequency boards is 90% complete.

3. PC-CORREL -
   • a simple program to test the simulator has been written which now works after inverting some of the logic.
   • PC-CORREL can now reset and start the correlator,
   • simple strobed I/O does not work yet because the correlator uses level and the PC14B interface edge driven input strobes, Some one-shot triggers need to be added to the interface wiring.
   • a long interface cable has been made and PC-COREL has been installed in its likely final position.

4. System software -
   • Two prototype graphical user interfaces have been written using Tk/Tcl:
     1. datool for doing backups on the DAT from Linux,
     2. dscan a prototype graphical user interface for doing drift scan observations,

1. PC-STEER hardware cage -
   • The analog/digital prototype card is being tested.
   • The digital/analog prototype is being constructed.

2. PC-STEER software -
   • a dynamically-loadable device driver for the hardware cage is operational. This includes reading and writing to the cage and setting the computer clock directly from the timer card of the cage on every read cycle (between 10 and 100 Hz),
   • all STEER coordinate calculations will be done offline and not in interrupt loop of the device driver,
   • All the STEER configuration data will be stored in the device server static database.

3. Fast data acquisition -
   • the voltage/frequency board layout is complete. A batch of between 10 and 20 boards is to be ordered.

4. PC-CORREL -
   • a one-shot has been installed on the appropriate strobe lines in the interface.
   • it is now possible to read back real data from the correlator using the PC-CORREL interface but the data still needs to be decoded to check that all is working as originally designed.
   • diagnostic software is being added,
   • the present software forms the basis of the test software which will be used to test the correlator in stand-alone mode,

5. System software -
   • it has demonstrated that the network time protocol (NTP) software which synchronises the computer clock using clock references in the Internet is (and was) working correctly - time is correctly synchronised to millisecond accuracy to the timer card in the PC-STEER cage. NTP will be used to keep all the server clocks synchronised.
   • Coding of the prototype scheduler has started.

1. PC-STEER hardware cage -
   • the digital/analogue board has been laid out and sent off for manufacture. A first batch of 7 has been ordered.
   • the encoder board prototype will be ready soon and a preliminary layout has already been done.
   • all other boards have been finalised.

2. PC-STEER software -
   • a blocking read + write have been implemented in the STEER cage device driver,
   • the driver + client can run at 100 Hz without loss of data, but this is dependant on system load ie X-windows.
   • the next step is to implement the steer cycle, once this has been done the telescope can be driven, all that is needed is a suitable cable and the completed cage,

3. Fast data acquisition -
   • the voltage/frequency board has been sent off for manufacture. Cost will be approximately R800 for 15 boards; components are about R200 per board.

4. PC-CORREL -
   • the interface PC-CORREL <--> correlator is fully tested and works as designed.
   • due to the continuous plugging and unplugging of the correlator during the tests the correlator (as predicted) has become unreliable.
   • this has put pressure on the hardware to be able to read out the 15 status bits to determine whether the correlator is still working.

5. System software -
   • there are now generalised scripts for startup and shutdown of the NCCS control system.
   • a skeleton of the scheduler exists and can be used as a basis for the first usable version.

6. Device Servers -
   • work has begun on an example of a device server for the HP3330 frequency synthesizer.
   • the first version of the STEER device server is seen as a top priority.

1. PC-STEER hardware cage -
   • two more boards have been laid out and sent off for manufacture, the analogue/digital and encoder boards. A first batch of 7 apiece have been ordered, These boards should be ready next week.
   • 3 further boards (timer, digital input/output and counter) are ready to be sent off. Only the demultiplexor board still awaits completion,
   • a list of required components is being prepared. In this regard connectors to populate the spare cage motherboard have been purchased.
   • it was decided that all LED's should be green unless they indicate a failure mode where red will be used instead.

2. PC-STEER software -
   • encoder support had been added to the STEER device driver. The driver is thus complete apart from any fine-tuning. Implementation of the steer control cycle has not yet been started.
   • work has begun on the Steer Device Server. A suitable Device Class is being generated at present.

3. Fast data acquisition -
   • 15 shielded boxes for the voltage/frequency boards have been made up.
   • long term stability monitoring of the prototype V/F against a Fluke Voltmeter shows a +-200Hz variation on a value of 1,250,000Hz at a input voltage of 500mV ie. equivalent to a input variation of 80 uV !!

4. Device Servers -
   • the HP3330 device server is now running though the implementation needs further work in terms of generalisation to other frequency synthesizers.

1. STEER hardware cage -
   • boards for the digital/analogue, analogue/digital and encoder cards have been manufactured. The first cards are about 90% complete and will be ready for testing soon.
   • the last four boards (digital input/output, counter, clock/timer and demultiplexor) are laid out and ready and will be sent off for manufacture once the other boards have been tested.
   • the second hardware cage is half way to completion.
   • initial production numbers are
     • 7 digital/analogue cards
     • 7 analogue/digital cards
     • 10 encoder cards
     • 7 digital input/output cards
     • 10 counter cards
     • 4 clock/timer cards
     • 3 demultiplexor cards
     Components for all these cards are either in house or on order.

2. Fast data acquisition -
   • the first voltage/frequency converter has been completed and awaits testing. Parts for at least one more V/F are in house.

1. PC-STEER hardware cage -
   • The first Digital/Analogue, Analogue/Digital and two Encoder cards have been completed. The D/A and A/D cards still need to be tested.
   • The four outstanding boards (Digital I/O, Counter, Clock/Timer and Demultiplexor) have been sent off for manufacture. They will hopefully be back next week.
   • The second hardware cage is now complete apart from the card guide-rails.
   • In discussion it was clarified that the initial production run should be
     • 3 Analogue/Digital cards
     • 3 Clock/Timer cards
     • 11 Counter cards
     • 3 Demultiplexor cards
     • 3 Digital/Analogue cards
     • 3 Digital I/O cards
     • 7 Encoder cards
     to meet the requirements for the simplest PC-STEER cage together with suitable spares.

2. Fast data acquisition -
   • Two Voltage/Frequency boards have been completed. Tests have revealed a slight discrepancy near 0.5V input. A third V/F is being built to allow further investigation.
   • we may need to make use of the more expensive version of the V/F chip.

3. SDIO (Serialized Digital I/O) design -
   • The new SDIO circuit design has been completed and is now ready to be prototyped.
   • The RS232 <--> RS422 converter circuit remains to be done.

4. PC-STEER cage software -
   • The PC-STEER control loop software has been cleaned up and divorced from its Turbo Pascal origins. The next stage is to build in support for the new hardware cage interface.
   • A bug has been fixed in the hardware cage device driver that caused the date to be set incorrectly under some circumstances.

5. System software -
   • The standardisation and documentation of the present operating system layout of the two NCCS computers has been completed.

1. PC-STEER hardware cage -
   • The Digital/Analogue, Analogue/Digital and two Encoder cards are completed and working.
   • An intermittent fault had been detected on the Digital Input/Output prototype.
   • The Digital Input/Output, Counter, Clock/Timer and Demultiplexor boards have been received and the first card of each type has been completed. The Demultiplexor card is presently undergoing tests.

2. Fast data acquisition -
   • The slight defect near 0.5V is dependent on the Voltage/Frequency chip, and is well within the manufacturer's specifications. Tests revealed that the chip should be selected to match the particular V/F board. The defect is believed to be well below the noise level in the signals these V2F's will be used to measure.
   • A third V/F converter has been built during the tests.

3. SDIO hardware -
   • Prototyping of the new SDIO circuit is well advanced.
   • No further work had been done on the RS232 <--> RS422 signal converter.

4. PC-STEER cage software -
   • The PC-STEER control loop software has been interfaced to the new hardware cage. The software is now able to acquire date synchronously at 100Hz with the control loop running at 10Hz on the original i486 hardware. Integration tests will start on completion of the final hardware and of the interface cabling.

5. System software -
   • A graphical tool has been written, based on an original version created by A.Goetz, to perform standard backups onto DAT tape to cover all NCCS backup requirements.

1. PC-STEER hardware cage -
   • All the cards are now completed and, except for the Clock/Timer card, fitted with front panels.
   • The wiring of the STEER <--> Servo interface is in progress and should be completed this week.
   • The spare cage was now complete apart from interface wiring.

2. SDIO hardware -
   • The new SDIO remote module prototype is complete and working.
   • A protoype RS232 <--> RS422 signal converter has been completed and tested in circuit with the remote module.

3. PC-STEER cage software -
   • The Trace / Debugger module for the Linux STEER port has also been successfully ported from the Turbo Pascal original.
   • The problems with the setting of time by the STEER cage device driver appear to be taken care of by the NTP daemon. Only the system clock on STEER itself will need to be treated cautiously.

4. Other software -
   • The graphical backup tool DATOOL has been released for general usage.
   • The initial port of LINES, the Spectral Line Analysis program, is progressing well.
   • Network Time Protocol (NTP) daemons are now running on all Linux/Unix boxes on the local network disciplining the clocks to track the NASA time code based clock on STEER.

5. Phase 1 Timeline -
   • It was pointed out that no time had been allocated for the integration of the new Clock module into the system. A suitable item will be included into the timeline.
   • The present Phase1 timeline was otherwise accepted without comment.

6. Antenna Cabling -
   • The issue of cabling to / from the antenna was raised. After discussion it was decided that suitable fibre-optic cabling will be investigated by a sub-committee.

1. PC-STEER hardware cage -
   • The second cage including extra wiring has both been completed and undergone QA.
   • About a dozen cards have also been completed and are to be sent for QA soon.

2. SDIO hardware -
   • PCB layouts of the SDIO remote module and the RS232 <--> RS422 signal converter have been received from the manufacturer. One board of each type has been populated and is undergoing acceptance tests.
   • The 6N139 opto-isolators manufactured by OTC would not work in the circuit which had been designed around the equivalent HP chip. Further investigation showed that selecting the value of the speedup capacitor would solve the problem. The possibility of an exchange is to be investigated.
   • Construction of the SDIO modules is now one of the critical paths on the timeline. Production is to commence forthwith.

3. Noise Diode Controller (NDC) Hardware -
   • An initial prototype had been completed and tested but the designer is not happy with the design as it contained upwards of 50 ICs.
   • Using PIC microprocessors the chip count could be reduced to about 16. The purchase of suitable programming hardware/software for the PIC microprocessors was approved pending the production of a short motivation.

4. Optic Fibre Cabling -
   • The present requirements are very unclear and after discussion it was decided to draw up a list of all relevant signals these cables would need to carry.
   • The technicians at Potchefstroom University Gamma Ray Observatory have been contacted and a visit is to be arranged soon.

5. Station Clock Module -
   • The Truetime Clock module has arrived. After some modifications it produces standard NASA-36 time code as required by the STEER interface hardware.
   • The clock will be installed in the next week. Tests to confirm that the clock is working correctly will follow before integration into the station timing system commences.

6. STEER cage software -
   • J.Quick reported back on his trip to ESRF: The initial version of the Steer Device Server underwent QA by A.Goetz during the visit. Some cosmetic changes were suggested.

7. TACO System Software -
   • The official release of the ESRF control software TACO for Linux will be based on v2.0+ in the ELF binary format. Apparently the NASA field system will also be moving to ELF in the near future.
   • The initial Linux port of TACO from HartRAO was further ported to Linux v2.0+ during the visit to ESRF. Integration into the official release is expected shortly. A.Goetz is presently revising the makefiles etc. to make distributions of releases more intuitive.

8. Phase 1 Timeline -
   • The hardware for Phase 1 appears to be roughly on track apart from the NDC which is being delayed by the optic fibre cabling issue. This issue appears to be critical and needs to be settled forthwith.
   • A new version of the timeline is necessary to reflect current realities. A clear route on optic fibre cabling will be necessary before any accurate predictions will be possible.
   • It was requested that issues relevant to Phase 2 and beyond be addressed prior to the end of Phase 1 to avoid unnecessary delays.

NCCS - Latest Update (30/10/96) !